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| TOSHIBA TC5117400BSJ/BST-60/70 PRELIMINARY 4,194,304 WORD X 4 BIT DYNAMIC RAM Description The TC5117400BSJ/BST is the new generation dynamic RAM organized 4,194,304 word by 4 bits. The TC5117400BSJ/BST utilizes Toshiba's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC5117400BSJ/BST to be packaged in a 26/24 pin plastic SOJ (300mil), and 26/24 pin plastic TSOP (300mil). The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V 10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. Features * 4,194,304 word by 4 bit organization * Fast access time and cycle time * Single power supply of 5V 10% with a built-in VBB generator * Low Power - 605mW MAX. Operating - (TC5117400BSJ/BST-60) - 523mW MAX. Operating - (TC5117400BSJ/BST-70) - 5.5mW MAX. Standby * Outputs unlatched at cycle end allows twodimensional chip selection * Common I/O capability using "EARLY WRITE" operation * Read-Modify-Write, CAS before RAS refresh, RAS-only refresh, Hidden refresh, Fast Page Mode and Test Mode capability * All inputs and outputs TTL compatible * 2048 refresh cycles/32ms * Package TC5117400BSJ: SOJ26-P-300C TC5117400BST: TSOP26-P-300D Key Parameters TC5117400BSJ/BST ITEM -60 tRAC tAA tCAC tRC tPC RAS Access Time Column Address Access Time CAS Access Time Cycle Time Fast Page Mode Cycle Time 60ns 30ns 15ns 110ns 40ns -70 70ns 35ns 20ns 130ns 45ns 1. This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-export, directly or indirectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited. 2. LIFE SUPPORT POLICY Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba America, Inc. Life support systems are either systems intended for surgical implant in the body or systems which sustain life. A critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this data book is subject to change without prior notice. Furthermore, Toshiba cannot assume responsibility for the use of any license under the patent rights of Toshiba or any third parties. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 1 TC5117400BSJ/BST-60/70 Pin Name A0 ~ A10 RAS CAS WE OE I/O1~I/O4 VCC VSS Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input/Output Power (+5V) Ground Standard DRAM DR16040794 Pin Connection (Top View) 2 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Block Diagram Standard DRAM TC5117400BSJ/BST-60/70 Absolute Maximum Ratings ITEM Input Voltage Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current SYMBOL VIN VOUT VCC TOPR TSTG TSOLDER PD IOUT RATING -0.5~VCC+0.5 -0.5~VCC+0.5 -0.5~7.0 0~70 -55~150 260 900 50 UNIT V V V C C C mW mA NOTE 1 1 1 1 1 1 1 1 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 3 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Recommended DC Operating Conditions (Ta = 0 ~ 70C) SYMBOL VCC VIH VIL PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage MIN. 4.5 2.4 -0.5** TYP. 5.0 MAX. 5.5 VCC + 0.5* 0.8 UNIT V V V NOTE 2 2 2 *VCC + 2.0V at pulse width 20ns (pulse width is measured at VCC). **-2.0V at pulse width 20ns (pulse width is measured at VSS). DC Electrical Characteristics (VCC = 5V 10%, Ta = 0 ~ 70C) SYMBOL |CC1 PARAMETER OPERATING CURRENT Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC=tRC MIN) STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VIH) RAS ONLY REFRESH CURRENT Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS=VIH: tRC=tRC MIN.) FAST PAGE MODE CURRENT Average Power Supply Current, Fast Page Mode (RAS =VIL, CAS, Address Cycling: tPC=tPC MIN.) STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VCC-0.2V) CAS BEFORE RAS REFRESH CURRENT Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC=tRC MIN.) INPUT LEAKAGE CURRENT Input Leakage Current, any input (0V 3, 5 UNIT mA NOTE 3,4 5 |CC2 mA |CC3 mA 3, 5 |CC4 mA 3,4 5 |CC5 mA |CC6 |I (L) |O (L) VOH VOL A A V V 4 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Electrical Characteristics and Recommended AC Operating Conditions (VCC = 5V 10%, Ta = 0~70C) (Notes 6,7,8) TC5117400BSJ/BST SYMBOL PARAMETER MIN tRC tRMW tPC tPRMW tRAC tCAC tAA tCPA tCLZ tOFF tT tRP tRAS tRASP tRSH tRHCP tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH Random Read or Write Cycle Time Read-Modify-Write Cycle Fast Page Mode Cycle Time Fast Page Mode Read-Modify-Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge CAS to Output in Low-Z Output Buffer Turn-off Delay Transition Time (Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time from CAS Precharge (Fast Page Mode) CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time CAS Precharge Time Row Address Set-Up Time Row Address Hold Time Column Address Set-Up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-Up Time Read Command Hold Time Read Command Hold Time referenced to RAS 110 155 40 85 0 0 3 40 60 60 15 35 60 15 20 15 5 10 0 10 0 10 30 0 0 0 -60 MAX. 60 15 30 35 15 50 10,000 200,000 10,000 45 30 MIN 130 180 45 95 0 0 3 50 70 70 20 40 70 20 20 15 5 10 0 10 0 15 35 0 0 0 -70 MAX 70 20 35 40 15 50 10,000 200,000 10,000 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 14 15 9,14, 15 9,14 9,15 9 9 10 8 UNIT NOTES PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 5 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Electrical Characteristics and Recommended AC Operating Conditions (Cont) TC5117400BSJ/BST SYMBOL PARAMETER MIN tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tROH tOEA tOED tOEZ tOEH tODS tWTS tWTH tWRP tWRH Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data Set-Up Time Data Hold Time Refresh Period Write Command Set-Up Time CAS to WE Delay Time RAS to WE Delay Time Column Address to WE Delay Time CAS Precharge to WE Delay Time CAS Set-Up Time (CAS before RAS Cycle) CAS Hold Time (CAS before RAS Cycle) RAS to CAS Precharge Time CAS Precharge Time (CAS before RAS Counter Test Cycle RAS Hold Time referenced to OE OE Access Time OE to Data Delay Output buffer turn off Delay Time from OE OE Command Hold Time Output Disable Setup Time Write Command Set-up Time (Test Mode In) Write Command Hold Time (Test Mode In) WE to RAS Precharge Time (CAS before RAS Cycle) WE to RAS Hold Time (CAS before RAS Cycle) 10 10 15 15 0 10 0 40 85 55 60 5 10 5 20 10 15 0 10 0 10 10 10 10 -60 MAX. 32 15 15 MIN 15 15 20 20 0 15 0 45 95 60 65 5 15 5 30 10 15 0 15 0 10 10 10 10 -70 MAX 32 20 15 ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 13 13 13 13 13 12 12 UNIT NOTES 6 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Electrical Characteristics and Recommended AC Operating Conditions in the Test Mode TC5117400BSJ/BST SYMBOL PARAMETER MIN tRC tPC tRAC tCAC tAA tCPA tRAS tRASP tRSH tCSH tRHCP tCAS tRAL Random Read or Write Cycle Time Fast Page Mode Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Hold Time CAS Precharge to RAS Hold CAS Pulse Width Column Address to RAS Lead Time 115 45 65 65 20 65 40 20 35 -60 MAX. 65 20 35 40 10,000 200,000 10,000 MIN 135 50 75 75 25 75 45 25 40 -70 MAX 75 25 40 45 10,000 200,000 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns 9, 14, 15 9, 14 9, 15 9 UNIT NOTES Capacitance (VCC = 5V 10%, f = 1MHz, Ta = 0 ~ 70C) SYMBOL CI1 CI2 CO PARAMETER Input Capacitance (A0~A10) Input Capacitance (RAS, CAS, WE, OE) Input Capacitance (I/O1~I/O4) MIN MAX 5 7 7 PF UNIT PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 7 TC5117400BSJ/BST-60/70 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Standard DRAM DR16040794 14. 15. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. All voltages are referenced to VSS. ICC1, ICC3, ICC4, ICC6 depend on cycle rate. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed one or less while RAS=VIL. In case of ICC4, it can be changed once or less during a fast page mode cycle (tPC). An initial pause of 200s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. AC measurements assume tT=5ns. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. Measured with a load equivalent to 2 TTL loads and 100pF. tOFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-Modify-Write cycles. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; If tRWDtRWD (min.), tCWDtCWD (min.), tAWDtAWD (min.) and tCPWDtCPWD (min.), (Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. Operation within the tRCD (max.) limit insures that tRAC can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 8 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Timing Waveforms Read Cycle Standard DRAM TC5117400BSJ/BST-60/70 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 9 TC5117400BSJ/BST-60/70 Write Cycle (Early Write) Standard DRAM DR16040794 10 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Write Cycle (OE Controlled Write) Standard DRAM TC5117400BSJ/BST-60/70 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 11 TC5117400BSJ/BST-60/70 Read-Modify-Write Cycle Standard DRAM DR16040794 12 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Fast Page Mode Read Cycle Standard DRAM TC5117400BSJ/BST-60/70 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 13 TC5117400BSJ/BST-60/70 Fast Page Mode Write Cycle (Early Write) Standard DRAM DR16040794 14 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Fast Page Mode Read-Modify-Write Cycle Standard DRAM TC5117400BSJ/BST-60/70 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 15 TC5117400BSJ/BST-60/70 RAS Only Refresh Cycle Standard DRAM DR16040794 CAS Before RAS Refresh Cycle 16 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Hidden Refresh Cycle (Read) Standard DRAM TC5117400BSJ/BST-60/70 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 17 TC5117400BSJ/BST-60/70 Hidden Refresh Cycle (Write) Standard DRAM DR16040794 18 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Outline Drawings (SOJ26-P-300C) Standard DRAM TC5117400BSJ/BST-60/70 Unit in mm PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 19 TC5117400BSJ/BST-60/70 Outline Drawings (TSOP26-P-300D) Standard DRAM DR16040794 Unit in mm 20 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY Back to Memory |
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